Conventional content addressable memory (CAM) devices use two known methods of initiating and controlling parity check operations. A first method operates the CAM device at a higher internal operating rate than that of a supplied clock or control signal to allocate parity checking time. An internal parity engine performs parity operations using additional “hidden” cycles caused by the higher internal clock rate. The number of hidden cycles defines the time available for parity checking operations.
In the first method, a user loses an ability to cause the CAM device to perform parity check operations deterministically. To increase a frequency of the parity check operation selection, the user must stop critical control inputs in order to artificially create the internal hidden cycles. Furthermore, the user may not be able to control the frequency of operation selection during normal operations. The frequency of operation selection is typically hardwired as a difference between the supplied or external frequency and the internal operating frequency.
Referring to FIG. 1, a block diagram of another conventional method of operating the CAM device for parity checking is shown. In the second method, a user device 6 stops or delays normal operation of a CAM device 8 by providing an idle instruction 10 within a stream of other instructions 12a–d to a CAM core 14. An internal parity engine 16 can then use the idle instruction time to perform a parity checking operation 18. The idle instruction cycles are considered “no-op” cycles and depend upon a design of the CAM device 8. The number of idle instruction cycles also defines the time available for parity checking operations 18.
In the second method, the user device 6 must stop normal operations to allow for the idle instruction cycles. Stopping normal user operations implies an addition of control circuitry in the user device 6 that can stall the issuing of new CAM device instructions for a proper duration and at a proper frequency. The user device 6 must also tolerate the stall. In addition, the number of idle cycles must be taken into account by the user device 6 before issuing the next instruction. However, the number of idle cycles required to complete the parity check operations can change from CAM device implementation to implementation and can depend on the frequency of the parity check operations.